Gate Dielectric Stack Benchmarking in Sub-3 nm FinFET vs. Gate-All-Around Nanosheet FETs: Trade-offs in Interface Trap Density, EOT Scaling, and NBTI Degradation Kinetics

Abstract

As CMOS technology nodes push below 3 nm, the selection of high-κ gate dielectric architectures in FinFET and gate-all-around (GAA) nanosheet field-effect transistors (NSFETs) presents critical trade-offs between equivalent oxide thickness (EOT) scaling, interface trap density (Dit), and negative bias temperature instability (NBTI) reliability. This study systematically benchmarks HfO₂-based and HfZrOₓ-based dielectric stacks integrated with TiN metal gates across both device topologies under accelerated aging conditions at 125 °C. Employing charge pumping spectroscopy, time-dependent dielectric breakdown (TDDB) analysis, and capacitance–voltage profiling, we demonstrate that GAA NSFETs exhibit a 23% lower Dit at the Si/SiO₂ interfacial layer compared to FinFET counterparts, while FinFETs retain superior NBTI recovery characteristics at equivalent EOT. These findings provide quantitative design guidelines for process engineers targeting sub-3 nm logic nodes.