Reconsidering Threshold Voltage Roll-Off in Sub-3nm Gate-All-Around Nanosheet FETs: Quantum Confinement Penalties Versus Classical DIBL Suppression Trade-offs

Abstract

Gate-all-around (GAA) nanosheet field-effect transistors have emerged as the presumed successor to FinFET architectures at sub-3nm technology nodes; however, prevailing compact models inadequately account for the interplay between quantum confinement-induced subband splitting and drain-induced barrier lowering (DIBL) suppression mechanisms. This work presents a rigorous re-examination of threshold voltage (Vth) roll-off behavior through self-consistent Schrödinger–Poisson simulations coupled with non-equilibrium Green's function (NEGF) transport formalism. Parametric sweeps across nanosheet width (3–8 nm) and gate dielectric permittivity reveal that conventional threshold voltage extraction methodologies overestimate electrostatic integrity by 12–19% under strong quantum confinement regimes. Revised figures of merit for multi-stack nanosheet configurations are proposed, offering corrected scaling guidelines for next-generation VLSI design at advanced technology nodes.