Mitigating Substrate Coupling-Induced Phase Noise Degradation in Millimeter-Wave LC-VCOs Through Deep N-Well Guard Ring Topology Optimization
Keywords:
LC voltage-controlled oscillator, substrate coupling suppression, millimeter-wave CMOS, phase noise, deep N-well guard ring, 60 GHz oscillator, figure-of-merit optimization, bulk CMOS substrate modeling, periodic steady-state noise analysisAbstract
Substrate coupling remains one of the most persistent sources of phase noise degradation in millimeter-wave LC voltage-controlled oscillators (LC-VCOs) fabricated in bulk CMOS technologies. This paper presents a systematic methodology for characterizing and suppressing substrate-borne interference using optimized deep N-well guard ring geometries integrated within a 28 nm bulk CMOS process node. Electromagnetic co-simulation combining finite-element substrate modeling with Spectre RF periodic steady-state (PSS) noise analysis was employed to quantify coupling attenuation as a function of guard ring segmentation density and well contact pitch. The proposed topology achieves a phase noise reduction of 9.4 dBc/Hz at a 1 MHz offset from a 60 GHz carrier, with a figure-of-merit (FoM) improvement of 6.1 dB over conventional single-ring guard structures, while maintaining a tuning range of 11.3% and a DC power consumption of 18.7 mW.
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