Gate Dielectric Stack Engineering in GaN-on-Si HEMTs vs. SiC-Based MOS-HEMTs: A Trade-off Evaluation of Breakdown Voltage, Threshold Voltage Stability, and Interface Trap Density
Keywords:
GaN-on-Si HEMT, SiC MOS-HEMT, gate dielectric stack, interface trap density, threshold voltage instability, breakdown voltage, Al₂O₃/HfO₂ bilayer, deep-level transient spectroscopy, power semiconductor devicesAbstract
This study presents a systematic comparative evaluation of gate dielectric stack configurations in gallium nitride-on-silicon (GaN-on-Si) high-electron-mobility transistors (HEMTs) and silicon carbide-based metal-oxide-semiconductor HEMTs (SiC MOS-HEMTs) targeting high-power switching applications. Al₂O₃/HfO₂ bilayer and single-layer SiO₂ gate dielectrics were benchmarked against thermally grown gate oxides under identical biasing and thermal stress conditions. Capacitance–voltage profiling, pulsed I–V characterization, and deep-level transient spectroscopy (DLTS) were employed to quantify interface trap density (Dit), threshold voltage instability (ΔVth), and off-state breakdown voltage (BVDS). GaN-on-Si devices exhibited superior electron mobility retention at elevated temperatures, whereas SiC MOS-HEMTs demonstrated lower Dit values and enhanced threshold voltage stability under repetitive gate stress cycling. These results provide device engineers with actionable selection criteria for next-generation power conversion modules.
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